Delay Fault Simulation

Abstract

As with any other fault model, delay fault simulation requires less computational effort than delay fault test generation. Therefore, after a test is generated fault simulation should be performed to cover as many faults as possible with the same test. Delay fault simulation can also be performed with functional, random, stuck-at or any other available set of vectors to determine the delay fault coverage and reduce the delay test generation effort. This chapter discusses methodologies for simulating transition, gate, path and segment delay faults in combinational and sequential circuits.