Abstract
Unlike stuck-at fault testing, delay testing is closely tied to the test application strategy. This means that before tests for delay faults are derived it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.
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© 1998 Springer Science+Business Media New York
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Krstić, A., Cheng, KT. (1998). Test Application Schemes for Testing Delay Defects. In: Delay Fault Testing for VLSI Circuits. Frontiers in Electronic Testing, vol 14. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5597-1_2
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DOI: https://doi.org/10.1007/978-1-4615-5597-1_2
Publisher Name: Springer, Boston, MA
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