Abstract
Semiconductor manufacturing process technology continues to progress relentlessly. The 1997 release of the SI A roadmap predicts 0.15μm process technology, with the potential to integrate 40 million transistors on logic chips, for the year 2001 [Asso97]. The acceleration of the introduction of process technologies is evident from the fact that the 1994 release of the SIA roadmap predicted only 0.18 m process technology for 2001 [Asso94]. As was recently pointed out [Nepp98] that the semiconductor industry may reach the limits of silicon technology. Today, however, this date appears to be well into the future. Structures that were thought to be impossible using traditional lithography are being routinely fabricated in 0.25 m fabs already. The introduction of 300mm wafers is well on its way.
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Notes
While VSI-A did not succeed in defining a single (or a few) on-chip-bus, within one company this is a more reasonable goal. Nevertheless, to allow e.g. peripherals to be used with multiple bus interfaces, we design them with a generalized point-to-point interface. This is supplemented by adaptors for the different supported busses. This approach is similar to the one that VSI-A adopted later on.
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© 1999 Springer Science+Business Media Dordrecht
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Schlichtmann, U., Wurth, B. (1999). An Integrated Approach Towards a Corporate Design Reuse Strategy. In: Seepold, R., Kunzmann, A. (eds) Reuse Techniques for VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5159-1_4
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DOI: https://doi.org/10.1007/978-1-4615-5159-1_4
Publisher Name: Springer, Boston, MA
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