Abstract
This chapter presents the dynamic semantics of a VHDL description as a declarative definition of the state space evaluated by the description. The state space consists of the values of declared signals and ports in the description.1 Since the net result of evaluating a VHDL description is reflected in the changes in values of its signals, the ‘waveforms’ of signals represent a semantics of the description. Thus, the ultimate goal in the definition of the semantics is to specify a set of time intervals spanning the entire simulation of the given VHDL description and to define the values of all signals in the description in those time intervals. The model presented herein is called the Dynamic Model and is based on the normal form of the Static Model as defined in Chapter 5.
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Notes
Files also form a part of the state space but they are not covered in this work.
The term virtual time was coined by Jefferson [28] to refer to simulation time in his description of the Time Warp paradigm for synchronizing parallel discrete event simulations.
It is assumed that simulation does not stop at any time.
The only case when they may not be equal is that of arrays which are not characterized herein.
The time intervals should be chosen such that the value of the signal is constant during the interval.
t has been chosen to be a delta interval for the sake of convenience.
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© 1999 Springer Science+Business Media New York
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Umamageswaran, K., Pandey, S.L., Wilsey, P.A. (1999). The Dynamic Model. In: Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5123-2_8
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DOI: https://doi.org/10.1007/978-1-4615-5123-2_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7331-5
Online ISBN: 978-1-4615-5123-2
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