The Static Model

Abstract

This chapter presents a mathematical representation of the static constructs of VHDL. This representation is referred to as the Static Model. The Static Model ignores the elaboration process and assumes that the given VHDL description has been fully elaborated and has correct syntax. It is not one-to-one with VHDL. In fact, many elements of VHDL do not appear in the model. For example, design entities are not presented in the model. They are not necessary. The model need only maintain the leaf level components (e.g., concurrent statements and their constituent subparts) and the netlist specifying their interconnections (i.e., the port hierarchy). In some instances not all of the leaf components that might be expected are present. For example, one might reasonably expect to see a tuple definition for concurrent signal assignment. However, such a tuple definition does not exist; instead, the concurrent signal assignment statement is represented using two distinct tuples, namely the selected concurrent signal assignment and the conditional concurrent signal assignment. This decomposition is easier to formally manipulate and the respective forms have distinct translations to process statements.