Background

Abstract

The design of the memory subsystem has received considerable attention among computer designers because of the crucial role played by memory in processor-based computation: the execution of every single instruction involves one or more accesses to memory. With the explosion of the memory requirements of application programs and the outpacing of the memory access speeds by processor speeds, the memory interface quickly became a major bottleneck. Since a larger memory implies a slower access time to a given memory element, computer architects have devised a memory hierarchy, consisting of several levels of memory, where higher levels comprise larger memory capacity and hence, longer access times. The memory hierarchy operates on the principle of locality of reference: Programs tend to reuse instruction and data they have used recently [HP94]. Thus, the first time an instruction or data is accessed, it might have to be fetched from a higher memory level, incurring a relatively higher memory access time penalty. However, it can now be stored in a lower memory level, leading to faster retrieval on subsequent accesses to the same instruction or data.