Abstract
In VHDL, the interface for a design is specified by the ENTITY declaration.
The ENTITY declaration specifies the input, output, and bi-directional signals that the design uses to communicate with external models. The ENTITY declaration also specifies any GENERIC values that can be used to parameterize the model.
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© 1999 Springer Science+Business Media New York
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Elliott, J.P. (1999). Entities, Architectures, and Processes. In: Understanding Behavioral Synthesis. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5059-4_5
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DOI: https://doi.org/10.1007/978-1-4615-5059-4_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7300-1
Online ISBN: 978-1-4615-5059-4
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