Abstract
The combination of VLSI process technology and Real-time Signal Processing (RSP) has brought a breakthrough in information technology (IT). The merging of computers, consumer and communication disciplines gives rise to very fast growing markets for personal communication, multi-media and broadband networks. Rapid evolution in sub-micron process technology allows ever more complex systems to be integrated on one single chip. Technology advances are however not followed by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs) and consumer markets. A consistent design technology that can cope with such complexity and with the ever shortening time-to-market requirements is of crucial importance [Tuck 97]. This design technology should support the realization of such digital VLSI systems for real-time information processing. It must encompass the methodology for designing such systems as well as the computer-aided design (CAD) tools and hardware/software libraries. Additionally, high-level behavioral models capturing the system behavior in an abstract and un-biased way are required allowing design space exploration and optimization. The real-time aspect of these RSP algorithms and of their implementation has not been given sufficient consideration.
“By the year 2005, a designer will have to achieve a design productivity of one 16-bit processor per day if he wishes to satisfy market demand ...”
—[anonymous]
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Notes
hard RT timing constraints are constraints that must be met absolutely, on penalty of catastrophic results. Soft RT constraints may occasionally be missed without troubling the integrity of the system [Marwedel 96] [Zalewski 93].
i.e. a processor interrupt, enabling to asynchronously activate the behavior in the ISR routine. See [Thoen 93a] for a discussion on interrupt related processor characteristics.
A well-known example of this is the (operation-level) scheduling step. For real-time data flow dominated applications, usually a list of force directed scheduler type algorithm is used. The list scheduling class (see e.g. [Goossens 87]) is better matched to dealing with strict resource constraints, the force-directed techniques (see e.g. [Paulin 89]) allow to better balance the data flow in a given time budget when (almost) no resource constraints are present. Finally, for control-dominated applications, the path scheduling type provides a good option because it can deal well with conditional traces exhibiting largely varying critical paths.
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© 2000 Springer Science+Business Media Dordrecht
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Thoen, F., Catthoor, F. (2000). Introduction. In: Thoen, F., Catthoor, F. (eds) Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4437-1_1
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DOI: https://doi.org/10.1007/978-1-4615-4437-1_1
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