Abstract
The basic principles of operation of a synchronous digital VLSI system are described in Chapter 2. As demonstrated in Chapter 3, the propagation of signals through logic gates and interconnections requires a certain amount of time to complete. Therefore, a timing discipline is necessary to ensure that logical computations—whether executing concurrently or in sequence—operate on the proper data signals. As described in Chapter 4, this timing discipline is implemented by inserting storage elements, or registers, throughout the circuit. Also analyzed in Chapter 4 are the timing relationships among signals in local data paths based on the type of clock signal and storage element. Recall from Chapter 4 the relationships that must be satisfied in order for a local data path to operate properly [inequalities (4.8), (4.13), (4.23), (4.24), and (4.29)]. These relationships are written in the form of bounds on the clock skew T Skew in order to emphasize that bounds are imposed on T Skew by various parameters of the data paths and the clock signal. If any of the inequalities, (4.8), (4.13), (4.23), (4.24), or (4.29), is not satisfied, a timing violation occurs.
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Notes
Propagating through a sequence of logic elements only.
Note that technically, TSkew(i, j) can be calculated for any ordered pair of registers 〈Rj, Rj〉. However, the skew between a non-sequential pair of registers has no practical value.
Later in Section 5.2.2 it is shown that it is more appropriate to refer to the permissible range of a sequentially-adjacent pair of registers. There may be more than one local data path between the same pair of registers but circuit performance is ultimately determined by the permissible ranges of the clock skew between pairs of registers.
As a matter of fact, the graph model described here is quite universal and can be successfully applied for a variety of other different circuit analysis and optimization purposes.
In the order in which the traveling signals pass through the gates.
Restrictions on the model itself and not on the ability of the model to represent features of the circuits.
Positive clock skew may also be thought of as increasing the path delay. In either case, positive clock skew (TSkew > 0) increases the difficulty of satisfying (5.5).
Equivalently, it is required that the clock signal arrive at each register at approximately the same time.
The number of registers N in the circuit.
Compared to the minimum possible clock period if zero skew is used throughout a circuit.
If the register is not a multi-bit register, this index is omitted.
As described previously in this chapter, clock skew can be thought of as adding (or subtracting) to (or from) the path delay.
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© 2000 Springer Science+Business Media New York
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Kourtev, I.S., Friedman, E.G. (2000). Clock Scheduling and Clock Tree Synthesis. In: Timing Optimization Through Clock Skew Scheduling. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4411-1_5
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DOI: https://doi.org/10.1007/978-1-4615-4411-1_5
Publisher Name: Springer, Boston, MA
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