Abstract
In order to understand the timing characteristics of a synchronous digital system—specifically, the delays within the data paths and clock distribution network—a more complete understanding of the properties of signal delay in VLSI systems is necessary. The topic of signal delay in VLSI-based systems is examined in detail in this chapter. Delay metrics are first analyzed and certain definitions are introduced in Section 3.1. A more thorough analytical treatment of the subject of computing delay in CMOS integrated circuits is presented in Section 3.2.
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Notes
Although the delay can be defined from any point X to any other point Y, the points X and Y typically correspond to an input and an output of a logic gate, respectively. In such a case, the signal delay from X to Y is the propagation delay of the gate.
Also, a gate may have asymmetric signal paths, whereby a gate would switch faster in one direction than in the other direction.
MOSFET ≡ Metal-Oxide-Semiconductor Field Effect Transistor
Derivation of the PMOS I–V equations is straightforward by accounting for the changes in voltage and current directions.
Typically, device channel length is chosen to be the minimum geometry permitted by the technology and therefore cannot be decreased to further increase β.
I, II, III, IV, and V for slower input signals.
Short-channel MOS devices in general.
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© 2000 Springer Science+Business Media New York
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Kourtev, I.S., Friedman, E.G. (2000). Signal Delay in VLSI Systems. In: Timing Optimization Through Clock Skew Scheduling. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4411-1_3
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DOI: https://doi.org/10.1007/978-1-4615-4411-1_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6985-1
Online ISBN: 978-1-4615-4411-1
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