Abstract
Our proposed overall co-synthesis flow is shown in Figure 7.1. The CDFG is built after performing the FFG task representation architecture independent optimizations, as well as the architecture dependent AFFG optimizations, followed by the optimal mapping step. After the AFFG is mapped onto an optimized CDFG we proceed with reactive synthesis. In the next section, we describe the CDFG representation, and the hardware and software co-synthesis techniques of the Polis co-design tool. A design environment based on hardware / software co-synthesis allows the designer to specify the system in a high level formal language (e.g. Esterel [16] front-end that our flow uses) by describing the functionality of each block and how blocks are connected together.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer Science+Business Media New York
About this chapter
Cite this chapter
Tabbara, B., Tabbara, A., Sangiovanni-Vincentelli, A. (2000). Hardware/Software Co-Synthesis and Estimation. In: Function/Architecture Optimization and Co-Design of Embedded Systems. The Springer International Series in Engineering and Computer Science, vol 585. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4359-6_7
Download citation
DOI: https://doi.org/10.1007/978-1-4615-4359-6_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6959-2
Online ISBN: 978-1-4615-4359-6
eBook Packages: Springer Book Archive