Abstract
Two VLSI testable architectural synthesis methodologies with testability, area, and delay constraints are presented in this chapter. This research differs from other synthesizers by
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1)
implementing testability as of the synthsizad VLSI arvchitectural solution,
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2)
providing feedback to the synthesis process, and
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3)
by integrating test incorporation with architectural synthesis(specifi-cally allocation and binding) using tree data structure.
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© 1991 Springer Science+Business Media New York
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Gebotys, C.H., Elmasry, M.I. (1991). The Catree Architectural Synthesis with Testability. In: Optimal VLSI Architectural Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 158. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4018-2_12
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DOI: https://doi.org/10.1007/978-1-4615-4018-2_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6797-0
Online ISBN: 978-1-4615-4018-2
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