Abstract
The global VLSI (very large scale integration) systems design cycle is briefly discussed below with respect to relationships between design stages, bottlenecks, and current open issues for design automation (DA). The design cycle involves moving from an abstract design specification to gradually a more detailed single or multichip design that can be tested and fabricated. The VLSI design stages are very interdependent and therefore it is important to outline the purpose of each stage before one can address the problems of high level synthesis. Area, power, speed, timing issues, input and output pin limitations, testability, and many other criteria are important in the design process. Interfaces to other complex processes, design complexity with respect to implementation technologies and testability will also be discussed. In addition, an understanding of the current computer aided-design (CAD) bottlenecks and open issues will further emphasize the importance and impact of high level architectural synthesis (the focus of this text) on the VLSI design cycle.
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© 1992 Springer Science+Business Media New York
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Gebotys, C.H., Elmasry, M.I. (1992). Global VLSI Design Cycle. In: Optimal VLSI Architectural Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 158. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4018-2_1
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DOI: https://doi.org/10.1007/978-1-4615-4018-2_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6797-0
Online ISBN: 978-1-4615-4018-2
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