Skip to main content
  • 62 Accesses

Abstract

This paper presents an efficient scheme for compiling monolithic arrays in scientific computation programs written in functional/applicative languages. In particular, the scheduling of code blocks (or loops) defining monolithic arrays on a pipelined dataflow computer is studied. A general framework for fine-grain code scheduling in pipelined machines is developed which addresses both time and space efficiency simultaneously for loops typically found in generalpurpose scientific computation. This scheduling method exploits fine-grain parallelism through dataflow software pipelining. The compiler will perform loop optimization through limited balancing 1 of the program graph, while the instruction-level scheduling is done dynamically at runtime in a data-driven manner. Simulation results are presented for verifying the notion and power of limited balancing.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. W. B. Ackerman and J. B. Dennis. VAL — A Value-Oriented Algorithmic Language. Technical Report 218, Laboratory for Computer Science, MIT, 1979.

    Google Scholar 

  2. A. Aiken and A. Nicolau. Optimal loop parallelization. In Proc. of the 1988 ACM SIGPLAN Conf. on Programming Languages Design and Implementation, June 1988.

    Google Scholar 

  3. Arvind and D.E. Culler. Managing resources in a parallel machine. In J.V. Woods, editor, Fifth Generation Computer Architecture, pages 103–121, Elsevier Science Publishers, 1986.

    Google Scholar 

  4. D. Bernstein and I. Gertner. Scheduling expressions on a pipelined processor with a maximal delay of one cycle. ACM Transactions on Programming Languages and Systems, 11(1):57–66, Jan. 1989.

    Article  MathSciNet  MATH  Google Scholar 

  5. E.G. Coffman. Computer and Job-Shop Scheduling Theory. John Wiley and Sons, New York, 1976.

    MATH  Google Scholar 

  6. J.B. Dennis. Data flow for supercomputers. In Proceeding of 1984 CompCon, March 1984.

    Google Scholar 

  7. J.B. Dennis and G.R. Gao. An Efficient Pipelined Dataflow Processor Architecture. Technical Report TR-SOCS-88.06, School of Computer Science, McGill University, Montreal, Que., Feb. 1988.

    Google Scholar 

  8. J.B. Dennis, G.R. Gao, and K.W. Todd. Modeling the weather with a data flow supercomputer. IEEE Trans. on Computers, C-33(7):592–603, 1984.

    Article  Google Scholar 

  9. G. R. Gao. A Pipelined Code Mapping Scheme for Static Dataflow Computers. Technical Report TR-371, Laboratory for Computer Science, MIT, 1986.

    Google Scholar 

  10. G.R. Gao. Aspects of balancing techniques for pipelined data flow code generation. Journal of Parallel and Distributed Computing, 6:39–61, 1989.

    Article  Google Scholar 

  11. G.R. Gao. A Flexible Architecture Model for Hybrid Dataflow and Control-Flow Evaluation. ACAPS Technical Memo 07, School of Computer Science, McGill University, Montreal, Que., Jan. 1989.

    Google Scholar 

  12. G.R. Gao. A maximally pipelined tridiagonal linear equation solver. Journal of Parallel and Distributed Computing, 3(2):215–235, June 1986.

    Article  Google Scholar 

  13. G.R. Gao. Maximum Pipelining of Array Computation — A Data Flow Approach. Technical Report TR-SOCS-87.12, School of Computer Science, McGill University, Montreal, Que., Sept. 1987.

    Google Scholar 

  14. G.R. Gao and Z. Paraskevas. Compiling for dataflow software pipelining. In Proc. of the Second Workshop on Languages and Compilers for Parallel Computing, Illinois, Aug. 1989. To be published by Pitman in their series Monographs in Parallel and Distributed Computing.

    Google Scholar 

  15. G.R. Gao, R. Yates, J.B. Dennis, and L. Mulline. An efficient monolithic array constructor. In Proc. of the 3rd Workshop on Languages and Compilers for Parallel Computing, Irvine, CA, to be published by MIT Press, 1990.

    Google Scholar 

  16. M.R. Garey and D.S. Johnson. Computers and Intractability: A guide to the Theory of NP-Completeness. W.H. Freeman and Company, 1979.

    Google Scholar 

  17. P.B. Gibbons and S.S. Muchnik. Efficient instruction scheduling for a pipelined architecture. In Proc. of the ACM Symp. on Compiler Construction, pages 11–16, Palo Alto, Calif., June 1986.

    Google Scholar 

  18. J. Hennessy and T. Gross. Postpass code optimization of pipelined constraints. ACM Transactions on Programming Languages and Systems, 5(3):422–448, July 1983.

    Article  MATH  Google Scholar 

  19. P. Hudak. Conception, evolution, and application of functional programming languages. Computing Surveys, 21(3), Sept. 1989.

    Google Scholar 

  20. P.M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill Book Company, New York, 1981.

    MATH  Google Scholar 

  21. D.J. Kuck, R.H. Kuhn, D.A. Padua, B. Leasure, and M. Wolfe. Dependence graphs and compiler optimizations. In Proc. of the 8th ACM Symp. on Principles of Prog. Lang., pages 207–218, 1981.

    Google Scholar 

  22. S.Y. Kung, S.C. Lo, and P.S. Lewis. Timing analysis and optimization of VLSI data flow arrays. In Proc. of the 1986 International Conf. on Parallel Processing, 1986.

    Google Scholar 

  23. M. Lam. Software pipelining: An effective scheduling technique for VLIW machines. In Proc. of the 1988 ACM SIG-PLAN Conf. on Programming Languages Design and Implementation, pages 318–328, Atlanta, Georgia, June 1988.

    Google Scholar 

  24. J.R. Larus and P.N. Hilfinger. Register allocation in the SPUR Lisp compiler. In Proc. of the ACM Symp. on Compiler Construction, pages 255–263, Palo Alto, Calif., June 1986.

    Google Scholar 

  25. A. Nicolau, K. Pingali, and A. Aiken. Fine-Grain Compilation for Pipelined Machines. Technical Report TR-88-934, Department of Computer Science, Cornell University, Ithaca, NY, 1988.

    Google Scholar 

  26. C. V. Ramamoorthy and G. S. Ho. Performance evaluation of asynchronous concurrent systems using petri nets. IEEE Trans, on Computers, 440–448, Sept. 1980.

    Google Scholar 

  27. C. Ramchandani. Analysis of Asynchronous Concurrent Systems. Technical Report TR-120, Laboratory for Computer Science, MIT, 1974.

    Google Scholar 

  28. B.R. Rau and C.D. Glaeser. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proc. of the 14-th Annual Workshop on Microprogramming, pages 183–198, 1981.

    Google Scholar 

  29. S.K. Skedzielewski and J. Glauert. IF1: An Intermediate Form for Applicative Languages. Technical Report M-170, Version 1.0, Lawrence Livermore National Laboratory, 1985.

    Google Scholar 

  30. R.F. Touzeau. A FORTRAN compiler for the FPS-164 scientific computer. In Proc. of the ACM SIGPLAN ′84 Symp. on Compiler Construction, pages 48–57, June 1984.

    Google Scholar 

  31. J.D. Ullman. NP-complete scheduling problems. J. Comput. Syst. Sci., 10:384–393, 1975.

    Article  MathSciNet  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1991 Springer Science+Business Media New York

About this chapter

Cite this chapter

Gao, G.R. (1991). Compiling Issues of Monolithic Arrays. In: Mullin, L.M.R., Jenkins, M., Hains, G., Bernecky, R., Gao, G. (eds) Arrays, Functional Languages, and Parallel Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-4002-1_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-4002-1_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6789-5

  • Online ISBN: 978-1-4615-4002-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics