Abstract
The HAL (Hardware Allocator) system was Paulin’s thesis work at Carleton University. HAL includes scheduling, data path synthesis, and design iteration.
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References
Pierre G. Paulin and John P. Knight, “Algorithms for High-Level Synthesis”, IEEE Design and Test, pages 18–31, December 1989.
Pierre G. Paulin and John P. Knight, “Scheduling and Binding Algorithms for High-Level Synthesis”, Proc. of the 26th DAC, pages 1–6, June 1989.
Pierre G. Paulin and John P. Knight, “Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s”, IEEE Trans. on CAD, pages 661–679, June 1989.
Pierre G. Paulin, High-Level Synthesis of Digital Circuits Using Global Scheduling and Binding Algorithms, PhD Thesis, Dept. of Electronics, Carleton University, January 1988.
P.G. Paulin and J.P. Knight, “Force-Directed Scheduling in Automatic Data Path Synthesis”, Proc. of the 24th DAC, pages 195–202, June 1987.
P.G. Paulin, J.P. Knight, and E.F. Girczyc, “HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis”, Proc. of the 23rd DAC, pages 263–270, June 1986.
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© 1991 Springer Science+Business Media New York
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Walker, R.A., Camposano, R. (1991). Carleton’s HAL System. In: Walker, R.A., Camposano, R. (eds) A Survey of High-Level Synthesis Systems. The Springer International Series in Engineering and Computer Science, vol 135. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3968-1_6
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DOI: https://doi.org/10.1007/978-1-4615-3968-1_6
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