Abstract
The University of California at Irvine’s VHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis.
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References
Elke A. Rundensteiner, Daniel D. Gajski, and Lubomir Bic, “The Component Synthesis Algorithm: Technology Mapping for Register Transfer Descriptions”, Proc. of ICCAD’90, pages 208–211, November 1990.
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© 1991 Springer Science+Business Media New York
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Walker, R.A., Camposano, R. (1991). Univ. of California at Irvine’s VSS. In: Walker, R.A., Camposano, R. (eds) A Survey of High-Level Synthesis Systems. The Springer International Series in Engineering and Computer Science, vol 135. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3968-1_32
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DOI: https://doi.org/10.1007/978-1-4615-3968-1_32
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6772-7
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