Abstract
IIT Delhi’s synthesis system includes design iteration, scheduling and data path synthesis. See alsoUniv. of Kiel’s MIMOLA System—Marwedel is also involved with that system.
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References
M. Balakrishnan and P. Marwedel, “Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration”Proc. of the 26th DACpages 68–74, June 1989.
M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, and Jayanti C. Majithia, “Allocation of Multiport Memories in Data Path Synthesis”IEEE Trans. on CADpages 536–540, April 1988.
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© 1991 Springer Science+Business Media New York
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Walker, R.A., Camposano, R. (1991). IIT Delhi’s Synthesis System. In: Walker, R.A., Camposano, R. (eds) A Survey of High-Level Synthesis Systems. The Springer International Series in Engineering and Computer Science, vol 135. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3968-1_19
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DOI: https://doi.org/10.1007/978-1-4615-3968-1_19
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