Abstract
IBM’s V compiler produces Register- Transfer level designs, which can then passed on to the LSS system for logic synthesis. The V compiler includes scheduling and data path synthesis, and can produce high level software simulators for the designs. A subset of the language is used to produce YIF format output for IBM’s Yorktown Silicon Compiler and IBM’s HIS System.
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References
Viktors Berstis, “Cycle-Level Timing Constraints in Behavioral Hardware Descriptions”, inComputer Hardware Description Languages and their Applications (Proc. of the 9th Int. Conf. on CHDLs)John A. Darringer and Franz J. Rammig (Editors), pages 197–205, North Holland, June 1989.
Viktors Berstis, “The V Compiler: Automating Hardware Design”IEEE Design and Testpages 8–17, April 1989.
Viktors Berstis, Daniel Brand, and Ravi Nair, “An Experiment in Silicon Compilation”Proc. of ISCAS’85pages 655–658, June 1985.
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© 1991 Springer Science+Business Media New York
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Walker, R.A., Camposano, R. (1991). IBM’s V Compiler . In: Walker, R.A., Camposano, R. (eds) A Survey of High-Level Synthesis Systems. The Springer International Series in Engineering and Computer Science, vol 135. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3968-1_17
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DOI: https://doi.org/10.1007/978-1-4615-3968-1_17
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