Abstract
CAD technology has been very successful in the last ten years. CAD tools for layout and logic design have been exceptionally successful to the point that they dominate system and chip design methodologies throughout the industry in the U.S. and abroad. This widespread methodology consists of manually refining product specifications through system and chip architecture until the design is finally captured on the logic level and simulated. Standard—cell methodology and tools were developed for easy mapping of logic—level design into IC layout. Because of the huge investment in CAD tools, equipment and training, many people believe that this trend will continue by providing more sophisticated CAD tools for capture, simulation and synthesis of logic—level designs.
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© 1991 Springer Science+Business Media New York
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Gajski, D.D. (1991). Essential Issues and Possible Solutions in High-Level Synthesis. In: Camposano, R., Wolf, W. (eds) High-Level VLSI Synthesis. The Springer International Series in Engineering and Computer Science, vol 136. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3966-7_1
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DOI: https://doi.org/10.1007/978-1-4615-3966-7_1
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