Abstract
This chapter discusses some of the anomalies inherent in VHDL which are commonly encountered when using the language. By ‘anomalies‘ we mean obstructions which impede your ability to use the language to design or model useful circuits.
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References
“IEEE Standard 1076–1987 VHDL Language Reference Manual,” IEEE Inc., New York, 1988.
Lipsett, R. et al., VHDL: Hardware Description and Design, Kluwer Academic Publishers, New York, 1989.
Scott, K., “Modeling Guidelines for Efficient Simulation,” VHDL Users’ Group Fall 1989 Meeting, pp. 5–08–5–13, October, 1989.
“The Sense of the VASG”, VHDL Users’ Group Fall 1989 Meeting, October, 1989.
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© 1991 Springer Science+Business Media New York
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Scott, K. (1991). Anomalies in VHDL and How to Address Them. In: Harr, R.E., Stanculescu, A.G. (eds) Applications of VHDL to Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3964-3_7
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DOI: https://doi.org/10.1007/978-1-4615-3964-3_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6770-3
Online ISBN: 978-1-4615-3964-3
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