Abstract
This chapter is written to assist the applications engineer familiar with transmission line behavior in improving digital simulation by incorporating transmission line behavior into digital models. It describes an approach for simulating the combined digital logic-transmission line behavior and centers on the VHDL behav’oral models used to simulate transmission line effects that enable simuIation of of chip environments such as multichip modules and cards.
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References
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© 1991 Springer Science+Business Media New York
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Stanisic, B.R. (1991). Modeling of Transmission Line Effects in Digital Circuits. In: Harr, R.E., Stanculescu, A.G. (eds) Applications of VHDL to Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3964-3_2
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DOI: https://doi.org/10.1007/978-1-4615-3964-3_2
Publisher Name: Springer, Boston, MA
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Online ISBN: 978-1-4615-3964-3
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