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Abstract

The problem of detecting a fault in a general combinational circuit is NP-complete [5] and it is unlikely that a polynomial time algorithm exists for solving it. The non-polynomial time complexity here refers to the worst-case effort of test generation in a circuit. Consequently, it is of interest to identify circuits for which a polynomial time fault detection algorithm exists. The number of primary inputs and the number of signals in the digital circuit are generally considered as the the input size for the fault detection problem.

“In the theory of computation, there is general agreement that a problem should be considered intractable if it cannot be solved in less than exponential time. ... suppose that we have three algorithms whose time complexities are n, n3 and 2n. Assuming thattime complexity expresses execution time in microseconds, the n, n3 and 2n algorithms can solve a problem of size 10 instantly in 0.00001, 0.001 and 0.001 seconds, respectively. ... to solve a problem of only size 60, the 2n algorithm requires 366 centuries whereas the n and n3 algorithms require only 0.00006 and 0.216 seconds, respectively.” — H. Fujiwara in Logic Testing and Design for Testability,MIT Press(1985).

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References

  1. V. D. Agrawal and S. C. Seth. Test Generation for VLSI Chips. IEEE Computer Society Press, Los Alamitos, CA, 1988.

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  4. H. Fujiwara. Computational Complexity of Controllability/Observability Problems for Combinational Circuits. IEEE Transactions on Computers, C-39(6): 762–767, June 1990.

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© 1991 Springer Science+Business Media New York

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Chakradhar, S.T., Agrawal, V.D., Bushneil, M.L. (1991). Polynomial-time Testability. In: Neural Models and Algorithms for Digital Testing. The Springer International Series in Engineering and Computer Science, vol 140. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3958-2_11

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  • DOI: https://doi.org/10.1007/978-1-4615-3958-2_11

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