Abstract
This paper presents a VLSI cellular array dedicated to the processing of neural networks. Each cell of this array computes the algorithms devoted to a neuron of a back propagation neural network. Our approach consists in permitting only integer computations and limiting the number of synaptic weightstconnections a cell must manage. If necessary, the topology of the neural network is locally changed with the introduction of sub-neurons and so related partially connected sub-layers. These changes in the topology add new degrees of freedom in the weight space and then increase the number of training epochs necessary to obtain a behaviour similar to that of the initial network. In recall mode, a 64 x 64 cellular array runs the NETtalk text-to-speech network 4 times faster than the Warp, a 20 node systolic array which uses a layer-based parallelism, 52 times faster than the Connection-Machine-1 which uses a synaptic parallelism and more than 2600 times faster than a Vax 780 without any parallelism.
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Faure, B., Mazaré, G. (1991). A VLSI Implementation of Multi-Layered Neural Networks: 2-Performance. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_37
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_37
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