Abstract
This paper presents the design of a digital delay-insensitive neural network engine. Delay-insensitive circuits are asynchronous and works correctly regardless of delays caused by logic elements and wires. They are data driven which means that their operation speed is determined by average processing times in contrast to the worst case as in synchronous circuits. Since a delay-insensitive circuit does not include any global control signals, e.g. clocks, it will work as fast as the operation conditions and data allow, regardless of the size of the circuit. These features are very attractive for realizing large neural networks. The architecture of the engine is based on a systolic toroidal network, which is well suited for a delay-insensitive implementation.
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References
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© 1991 Springer Science+Business Media New York
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Nielsen, C.D., Staunstrup, J., Jones, S.R. (1991). A Delay-Insensitive Neural Network Engine. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_36
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_36
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