Abstract
Designing hardware requires a thorough decomposition of the conceptual models to be integrated as well as extensive analysis of all the functional parameters they involve. Together with an introduction to artificial neuron models, we briefly explain, in this paper, why artificial neural networks are good candidates for silicon integration although they still require much theoretical thoughts.
Analysis at the conceptual level and integration at the logic and gate levels, conducted in parallel, are intended to lead to a digital VLSI realization of Hopfield’s and Kohonen’s models. This paper develops an original architectural approach using semi-specialized recurrent systolic arrays building blocks to be combined in general neuro-emulators starting with those two well known models. These implementations are primarily intended to be used as preprocessing stage to real-time computing.
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© 1991 Springer Science+Business Media New York
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Lehmann, C., Blayo, F. (1991). A VLSI Implementation of a Generic Systolic Synaptic Building Block for Neural Networks. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_32
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_32
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