Abstract
This paper presents the hardware realization of a binary associative memory. Two designs have been made to provide dedicated VLSI chips. A cascadable architecture allows to build up associative systems consisting of several thousand neurons. To keep costs low and reach a high storing density, standard RAM chips are used for weight storage. The realizable memory systems may be used for arbitrary fast associations or for classification tasks. Due to high speed performance of the hardware, real time problems may be solved.
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References
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© 1991 Springer Science+Business Media New York
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Poechmueller, W., Glesner, M. (1991). A Cascadable VLSI Architecture for the Realization of Large Binary Associative Networks. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_26
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_26
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6671-3
Online ISBN: 978-1-4615-3752-6
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