Abstract
In this paper, we address the problem of designing a parallel system for the experimentation of arbitrary multilayered networks running the Boltzmann Machines algorithm. We present the Synchronous Boltzmann Machine, a new model recently introduced by Azencott (1989) and the functional analog cells its implementation requires. We then describe a fully analog cascadable chip set, already described, and introduce a new circuit which features internal analog computations and storage, and digital data I/O. We show how it can be used in a digital system performing the dynamical change of the network architecture.
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Garda, P., Belhaire, E. (1991). An Analog Circuit with Digital I/O for Synchronous Boltzmann Machines. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_24
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_24
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6671-3
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