Abstract
The unification task is one of the most complex and time-consuming activities in the execution of Prolog programs. The solutions currently implemented in Prolog machines are based on the sequential execution of Robinson’s based algorithms using some architectural supports to data tags testing and manipulation and to the intrinsic recursivity of the algorithm. In this work the application of associative techniques is evaluated inside a WAM environment and a detailed comparison is done with respect to the sequential solution. The structure of an incremental VLSI unifier, able to work properly with an existing Prolog processor, is derived from the analysis of experimental data.
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References
Civera, P., et al., “A 32 bit processor for Compiled Prolog”, VLSI for Artificial Intelligence, Kluwer Academic Publishers, pp.13–26 1989.
Civera, P., Piccinini, G., Zamboni,M., “Implementation Studies for a VLSI PROLOG Co-Processor”, IEEE MICRO, February 1989 Vol.9 No. 1.
Corbin, J., Bidoit, M., “A Rehabilitation of Robinson’s Unification Algorithm”, Information Processing 83, REA Mason (ed), Elsevier Science Publishers B.V., pp. 909–914, 1983.
Martelli, A., Montanari, U., “An Efficient Unification Algorithm”, ACM Transactions on Programming Languages and Systems, Vol. 4, No. 2, pp. 258–282, 1982.
Nakamura, K., “Associative concurrent evaluation of Logic Programs”, Journ. Of Logic Programming, Elsevier Science Publishers, pp. 109–118, 1989.
Ng, Y., Glover, R., Chng, C.L., “Unify with active memory”, VSLI for Artificial Intelligence, Kluwer Academic Publishers, pp. 109–118, 1989.
Oldfield, J., “Logic Programs and Experimental Architecture for their Execution”, Proceedings IEE, 133, Pt.E, No.3,May 1986, pp.163–167.
Oldfield, J., “Accelerating Programming System with the Aid of VLSI Components”, Tech. Rep. Computer Laboratory, University of Cambridge, 1987.
Oldfield, J., Stormon, C.D., Brule, M., “The Application of VLSI Content-Addressable Memories to the Acceleration of Logic Programming System”, COMPEURO 87 pp.27–30, 1987.
Paterson, M.S., Wegman, M.N., “Linear Unification”, Journal of Computer and Systems Sciences, pp.158–167, 1978.
Passatore, S., “Studio e valutazione di architetture associative per l’esecuzione di Prolog”, Graduation Thesis, Politecnico di Torino (I), 1990
Robinson, J.A., “A machine-oriented logic based on the resolution principle”, Journ. Ass. Comput. Mach., pp. 23–41, 1965.
Robinson, I., “A Prolog Processor based on a Pattern Matching Memory Device”, 3rd International Conference on Logic Programming,Springer-Verlag, pp. 172–179,1986.
Robinson, I., “The Pattern Addressable Memory: Hardware for Associative Processing”, VLSI for Artificial Intelligence, Kluwer Academic Publishers, pp.119–129 1989.
Shobatake, Y., Aiso H., “A Unification processor based on uniformly structured cellular hardware”, IEEE Proceeding on Computer Architecture, pp. 140–148, 1986.
Warren, D.H.D, “An abstract Prolog Instruction Set”, Technical Note 309, SRI, Menlo Park, CA 1983.
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© 1991 Springer Science+Business Media New York
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Civera, P.L., Masera, G., Piccinini, G.L., Roch, M.R., Zamboni, M. (1991). Performance Evaluation of a VLSI Associative Unifier in a WAM Based Environment. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_12
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_12
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