Abstract
Conventional microprocessors and RISC processors do not adequately support the implementaton of logic programming languages. This paper presents extensions of a RISC processors’s instruction set to enable a simplified and more efficient implementation of Prolog. The extensions are very general so that they can be used for most processors.
The first part of the paper gives a short introduction to Prolog implementation techniques. The most common abstract machines are the Warren Abstract Machine and the Vienna Abstract Machine. Both can be implemented using interpretative and compiling techniques. To enable efficient implementation the instruction set of RISC processors should be enhanced by instructions for sequential memory access,iństructions for tag handling and some special instructions. Those instructions can easily be added to existing processors without increasing the cycle time or the cycle count. The extensions are compared to existing microprocessors and special purpose hardware.
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References
Abe, S., Bandoh, T., Yamaguchi S., Kurosawa, K. and Kiriyama, K., “High Performance Integrated Prolog Processor IPP”, 14th Annual International Symposium on Computer Architecture,pp.100–107, 1987
Bell, J.R., “Threaded Code”, Communincations of the ACM, vol. 16(6), pp. 370–372, 1973
Borriello, G., Cherenson, A., Danzig, P. and Nelson, M., “RISCS vs. CISCS for Prolog: A Case Study”, Architectural Support for Programming Languages and Operating Systems, SIGPLAN 22(10), pp.136–145, 1987
Dobry, T.P., Patt, Y.N. and Despain, A.M., “Design Decisions Influencing the Microarchitecture for a Prolog Machine”, 17th Annual Microprogramming Workshop, New Orleans, pp.217–231, 1984
Edenfild, R., Gallup, M.G., Ledbetter, W.G., McGarity, R.C., Quintana, E.E. and Reininger, R.A., “The 86040 Processor”, IEEE Micro, pp.66–78, February 1990
Fagin, B., Patt, Y., Srini V. and Despain Alvin, “Compiling Prolog Into Microcode: A Case Study Using the NCR/32–000”, 18th Annual Workshop on Microprogramming, Pacific Grove, pp.79–88, 1985
Gee, J. Melvin, S.W. and Patt, Y.N., “Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer”, Logic Programming 87, Melbourne, pp.120, 1987
Kane, G., MIPS R2000 RISC Architecture, Englewood Cliffs, Prentice Hall,1987
Krall, A., “Implementation of a High-Speed Prolog Interpreter”, SIGPLAN ‘87 Symposium on Interpreters and Interpretative Techniques,St. Paul, pp.125–131,1987
Krall, A. and Neumerkel, U., “The Vienna Abstract Machine”, Programming Language Implementation and Logic Programming,Linköping, pp.121–135, 1990
Konagaya, A., Habata, S., Atarashi, A. and Yokota, M., “Performance Evaluation of a Sequential Inference Machine CHI”, Logic Programming 89, Cleveland, pp.1148–1164; 1989
Mills, J.W., “A High-Performance Low RISC Machine for Logic Programming”, Journal of Logic Programming, vol. 4, pp.179–212, 1989
Motorola, MC88100 User’s Manual, Motorola, 1988
Mulder, H. and Tick, E., “A Performance Comparison between PLM and a M68020 PROLOG Processor”, Logic Programming 87, Melbourne, pp.59–73, 1987
Nakashima, H. and Nakajima, K., “Hardware Architecture of the Sequential Inference Machine: PSI-II”, 1987 International Symposiium on Logic Programming,pp.104–113, 1987
Nakazaki, R. et al., “Design of a High-Speed Prolog Machine (HPM)”, 12th Annual International Symposium on Computer Architecture, pp.191–197, 1985
Patterson, D., “Reduced Instruction Set Computers”, Communications of the ACM, vol. 28(1), pp.8–21, 1985
Sun, The SPARC Architecture Manual, Sun, 1987
Tick, E. and Warren, D.H.D., “Towards a Pipelined Prolog Processor”, New Generation Computing,vol. 2, pp.323–345, 1984
Touati, H. and Despain, A., “An Empirical Study of the Warren Abstract Machine”, 1987 International Symposiium on Logic Programming,pp.114–124, 1987
Van Roy, P., “An Intermediate Language to Support Prolog’s Unification”, Logic Programming 89, Cleveland, pp.1148–1164, 1989
Warren, D.H.D., “An Abstract Prolog Instruction Set”, TR. 309 SRI International, 1983
Woo, N.S, “A Hardware Unification Unit: Design and Analysis”, 12th Annual International Symposium on Computer Architecture, pp.198–205, 1985
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© 1991 Springer Science+Business Media New York
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Krall, A. (1991). An Extended Prolog Instruction Set for RISC Processors. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_10
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_10
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