Abstract
This paper analyzes a new hardware solution for the cache coherence problem in large scale shared memory multiprocessors. The protocol is based on a linked list of caches — forming a distributed directory and does not require a global broadcast mechanism. Fully-mapped directory-based solutions proposed earlier also do not require a global broadcast mechanism. However, our solution is more scalable and provides potentially better performance than the fully-mapped directory-based protocol. We provide simulation results to show that the performance of the distributed directory protocol is more robust when there is contention for the data and for variations in memory technology. Further, we do not assume that the network preserves the order of messages. Thus we do not preclude adaptive routing.
This work was supported by equipment provided by the Knowledge Systems Laboratory, Department of Computer Science, Stanford University.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Anant Agarwal, Richard Simoni, John Hennessy, and Mark Horowitz. An evaluation of directory schemes for cache coherence. In Proceedings of the 15th International Symposium on Computer Architecture, pages 281–289, 1988.
James Archibald and Jean-Loup Baer. Cache coherence protocols: Evaluation using a multiprocessor simulation model. ACM Transactions on Computer Systems, 4(4):274–298, November 1986.
Sandra Johnson Baylor and Faye A. Briggs. The effects of cache coherence on the performance of parallel PDE algorithms in multiprocessors. In Proceedings of the 1989 International Conference on Parallel Processing, pages 233–236, 1989. Vol-I.
W.C. Brantley, K.P. McAuliffe, and J. Weiss. RP3 processor-memory element. In Proceedings of the 1985 International Conference on Parallel Processing, pages 782–789, 1985.
Greg Byrd. Personal communication regarding talk given by Tom Knight at a workshop on ultra large scale message passing computers, 1987.
Gregory Byrd, Nakul Saraiya, and Bruce Delagi. Multicast communication in multiprocessor systems. In Proceedings of the 1989 International Conference on Parallel Processing, pages 196–200, 1989. Vol-I.
Lucien M. Censier and Paul Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, c-27(12):1112–1118, December 1978.
Michel Dubois, Christoph Scheurich, and Faye Briggs. Memory access buffering in multiproceesors. In Proceedings of the 13th International Symposium on Computer Architecture, pages 434–442, 1986.
M. Odaka et.al. A 512Kb/5ns BiCMOS RAM with 1KG/150ps logic gate array. In Proceedings of the 1989 IEEE International Solid-State Circuits Conference, pages 28–29, 1989.
T. Takeshima et.al. A 55ns 16Mb DRAM. In Proceedings of the 1989 IEEE International Solid-State Circuits Conference, pages 246–247, 1989.
David V. James, Anthony T. Laundrie, Stein Gjessing, and Gurinder S. Sohi. Scalable coherent interface. IEEE Computer, 23(6):74–77, June 1990.
Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, and John Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. Technical Report CSL-TR-89-404, Computer Systems Laboratory, Stanford University, 1989.
Christoph Scheurich and Michel Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the 14th Interna-tional Symposium on Computer Architecture, pages 234–243, 1987.
Manu Thapar and Bruce Delagi. Design and implementation of a distributed directory cache coherence protocol. Technical report KSL-89-72, Stanford University, 1989.
Manu Thapar and Bruce Delagi. Stanford distributed-directory protocol. IEEE Computer, 23(6):78–80, June 1990.
Wolf-Dietrich Weber and Anoop Gupta. Analysis of cache invalidation patterns in multiprocessors. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 243–256, 1989.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1992 Springer Science+Business Media New York
About this chapter
Cite this chapter
Thapar, M., Delagi, B. (1992). Scalable Cache Coherence Analysis for Shared Memory Multiprocessors. In: Dubois, M., Thakkar, S. (eds) Scalable Shared Memory Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3604-8_8
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3604-8_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6601-0
Online ISBN: 978-1-4615-3604-8
eBook Packages: Springer Book Archive