Skip to main content

Locks, Directories, and Weak Coherence—a Recipe for Scalable Shared Memory Architectures

  • Chapter
  • 105 Accesses

Abstract

Bus based multiprocessors have the limitation that they do not scale well to large numbers of processors due to the bus becoming a bottleneck with the current bus technology. Lock-based protocols have been suggested as a possible way of mitigating this bottleneck for single bus systems with snooping ability. In this research, we are interested in extending lock-based protocols to general interconnection networks. Directory based cache coherence schemes have been proposed for such networks. We are investigating a combination of locking with directory based schemes. Further, most protocols in the literature until now, assume a strong coherence requirement. However, recent research has shown that it is possible to weaken this coherence requirement. Such an approach is expected to reduce the coherence overhead even further, making it an appealing one for building scalable systems.

This work is supported in part by NSF grant MIP-8809268

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. Archibald and J. Baer. Cache coherence protocols: evaluation using a multiprocessor model. ACM Transactions on Computer Systems, pages 278–298, Nov. 1986.

    Google Scholar 

  2. Y. Afek, G. Brown, and M. Merritt. A lazy cache algorithm. In Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pages 209–223, June. 1989.

    Google Scholar 

  3. S. V. Adve and M. D. Hill. Weak ordering—a new definition. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 2–11, May 1990.

    Google Scholar 

  4. P. Bitar and A. M. Despain. Multiprocessor cache synchronization: Issues, innovations, evolution. In Proceedings of the 13th Annual International Symposium on Computer Architecture, pages 424–433, June 1986.

    Google Scholar 

  5. E. D. Brooks. The Butterfly barrier. International Journal of Parallel Programming, pages 295–307, Aug. 1986.

    Google Scholar 

  6. J. Baer and W. Wang. Architectural choices for multi-level cache hierarchies. In Proceedings of the 1987 International Conference on Parallel Processing, pages 258–261, 1987.

    Google Scholar 

  7. D. Chaiken, C. Fields, K. Kurihara, and A. Agarwal. Directory-based cache coherence in large-scale multiprocessors. IEEE Computer, 1990.

    Google Scholar 

  8. D. A. Cheriton, H. A. Goosen, and P. D. Boyle. Multi-level shared caching techniques for scalability in VMP-MC. In Proceedings of the 16th Annual International Symposium on Computer Architecture, pages 16–24, June 1989.

    Google Scholar 

  9. K. Charachorloo, D. Lenoski, J. Laudon, and A. Gupta. Memory consistency and event ordering in scalable shared-memory multiprocessors. Technical Report CSL-TR-89-405, Stanford University, Computer Systems Laboratory, Nov. 1989.

    Google Scholar 

  10. M. Dubois, C. Scheurich, and F. Briggs. Memory access buffering in multiprocessors. In Proceedings of the 13th Annual International Symposium on Computer Architecture, pages 434–442, June 1986.

    Google Scholar 

  11. M. Dubois, C. Scheurich, and F. Briggs. Synchronization, coherence, and event ordering in multiprocessors. IEEE Computer, pages 9–21, Feb. 1988.

    Google Scholar 

  12. J. R. Goodman. Using cache memory to reduce processor-memory traffic. In Proceedings of the 10th Annual International Symposium on Computer Architecture, pages 124–131, June 1983.

    Google Scholar 

  13. J. R. Goodman and P. J. Woest. The Wisconsin Multic-ube: a new large-scale cache-coherent multiprocessor. In Proceedings of the 15th Annual International Symposium on Computer Architecture, pages 422–431, June 1988.

    Google Scholar 

  14. P. Hutto and M. Ahamad. Slow memory: Weakening consistency to enhance concurrency in distributed shared memory. Technical Report GIT-ICS-89/39, Georgia Institute of Technology, Oct. 1989.

    Google Scholar 

  15. IEEE P1596—SCI Coherence Protocols. Scalable Coherent Interface, March 1989.

    Google Scholar 

  16. R. H. Katz, S. J. Eggers, D. A. Wood, C. L. Perkins, and R. G. Sheldon. Implementing a cache consistency protocol. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 276–283, June 1985.

    Google Scholar 

  17. A. R. Karlin, M. S. Manasse, L. Rudolph, and D. D. Sleator. Competitive snoopy caching. Algorithmica, 3:79–119, 1988.

    Article  MathSciNet  MATH  Google Scholar 

  18. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9):690–691, September 1979.

    Article  Google Scholar 

  19. J. Lee and U. Ramachandran. Synchronization with multiprocessor caches. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 27–37, May 1990.

    Google Scholar 

  20. R. J. Lipton and J. S. Sandberg. PRAM: A scalable shared memory. Technical Report CS-TR-180-88, Princeton University, September 1988.

    Google Scholar 

  21. E. McCreight. The Dragon Computer System: An early overview. Xerox Corp., Sept. 1984.

    Google Scholar 

  22. T. N. Mudge, J. P. Hayes, and D. C. Winsor. Multiple bus architectures. Computer (USA), 20(6):42-48, June 1987.

    Google Scholar 

  23. C. D. Polychronopoulos. Parallel Programming and Compilers, pages 113–158. Kluwer Academic Publishers, 1988.

    Google Scholar 

  24. M. Papamarcos and J. Patel. A low overhead solution for multiprocessors with private cache memories. In Proceedings of the 11th Annual International Symposium on Computer Architecture, pages 348–354, June 1984.

    Google Scholar 

  25. C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 234–243, June. 1987.

    Google Scholar 

  26. C. P. Thacker and L. C. Stewart. Firefly: A multiprocessor workstation. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems, pages 164–172, Oct. 1987.

    Google Scholar 

  27. A. W. Wilson. Hierarchical cache/bus architecture for shared memory multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 244–252, June 1987.

    Google Scholar 

  28. P. C. Yew, N. F. Tzeng, and D. H. Lawrie. Distributing hot-spot addressing in large-scale multiprocessor. IEEE Transactions on Computers, pages 388–395, April 1987.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1992 Springer Science+Business Media New York

About this chapter

Cite this chapter

Lee, J., Ramachandran, U. (1992). Locks, Directories, and Weak Coherence—a Recipe for Scalable Shared Memory Architectures. In: Dubois, M., Thakkar, S. (eds) Scalable Shared Memory Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3604-8_4

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-3604-8_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6601-0

  • Online ISBN: 978-1-4615-3604-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics