Abstract
The memory reference trace of a parallel program is strongly dependent on the memory architecture and memory management policy environment. A change in that environment can change the addresses in the trace as well as the interleaving of the addresses. We have examined the issue of ensuring that the generated global trace is correct for the new environment. In this paper we summarize the key results and informally illustrate the proposed method using an example parallel program.
“This work was supported in part by the National Science Foundation (Grants CCR-8721781 and CCR-8821809).
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References
A. V. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, MA, 1986.
M.A. Holliday. Techniques for cache and memory simulation using address reference traces. Int. Journal of Computer Simulation. to appear.
M.A. Holliday and C.S. Ellis. Accuracy of memory reference traces of parallel computations in trace-driven simulation. Technical Report CS-1990-8, Dept. of Computer Science, Duke Univesity, Durham, NC, July 1990. submitted for publication.
L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9):690–691, September 1979.
Sequent Computer Systems, Inc. Balance 8000 Technical Summary. Sequent Computer Systems, Inc., 1986.
A. Smith. Cache evaluation and the impact of workload choice. In Proceedings of the 12th Annual International Symposium on Computer Architecture, Boston, MA, June 1985.
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© 1992 Springer Science+Business Media New York
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Holliday, M.A., Ellis, C.S. (1992). An Example of Correct Global Trace Generation. In: Dubois, M., Thakkar, S. (eds) Scalable Shared Memory Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3604-8_3
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DOI: https://doi.org/10.1007/978-1-4615-3604-8_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6601-0
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