Abstract
This article discusses the current status of the Scalable Coherent Interface (SCI), IEEE standards project P1596. The SCI cache coherence protocol is scalable (up to 64K processors can be supported), efficient (memory is not involved in the common pairwise-sharing updates), and robust (data can be reliably recovered by software after transmission errors). Scalability is achieved by having the memory directory identify only the first processor sharing a cache line; other processors sharing the same line are identified by entries in a distributed doubly linked list.
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© 1992 Springer Science+Business Media New York
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Gjessing, S., Gustavson, D.B., Goodman, J.R., James, D.V., Kristiansen, E.H. (1992). The SCI Cache Coherence Protocol. In: Dubois, M., Thakkar, S. (eds) Scalable Shared Memory Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3604-8_12
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DOI: https://doi.org/10.1007/978-1-4615-3604-8_12
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