Abstract
A transient state can be used to mark a cache lines for which an access have started, but not yet completed. It can be used to implement cache-coherence protocols for split transaction buses.
Transient states can also be used to implement nonblocking writes, i.e. the processor never stalls on a write, while providing processor consistency for a certain class of networks. This has earlier only been achieved for looser forms of consistency at an extra hardware cost.
The same technique can be used to resolve data dependencies at runtime, implementing a functionality similar to that of Dataflow’s I-structure memory, at no extra hardware cost.
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Hagersten, E., Landin, A., Haridi, S. (1992). Multiprocessor Consistency and Synchronization through Transient Cache States. In: Dubois, M., Thakkar, S. (eds) Scalable Shared Memory Multiprocessors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3604-8_10
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DOI: https://doi.org/10.1007/978-1-4615-3604-8_10
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