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Fabrication Techniques for Submicron Devices

  • David K. Ferry
  • Robert O. Grondin
Part of the Microdevices book series (MDPF)

Abstract

It is now possible to fabricate test patterns, which compose the basic parts of elemental semiconductor devices, that are as small as 10 nm in size, and to see individual features on the order of 1 nm in size.(1) This suggests that further device miniaturization and entirely new device concepts are certain to occur. However, coupled with the decrease in device size has been a concomitant increase in the number of devices that are contained on a single integrated circuit. Today’s 0.5-ikm devices allow as many as 16 million transistors on a single dynamic memory chip or as many as a million devices on a microprocessor chip. Therefore, while it is feasible to use exotic processing techniques to fabricate single devices, the industry requires processing techniques which can fabricate large arrays of chips, with each chip containing this large number of individual devices. Thus, the practicality of a particular process is of utmost importance if it is to be used in the continuing growth of integrated circuit density.

Keywords

Schottky Barrier Etch Rate Modulation Transfer Function Fabrication Technique Effective Barrier Height 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • David K. Ferry
    • 1
  • Robert O. Grondin
    • 1
  1. 1.College of Engineering and Applied Science Center for Solid State Electronics ResearchArizona State UniversityTempeUSA

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