A Real-Time Full Duplex 16/8 kbps CVSELP Coder with Integral Echo Canceller Implemented on a Single DSP56001

Abstract

The trend in today’s private digital networks is to integrate data with voice traffic. This offers considerable cost savings and convenience by allowing data and digitized voice to share the same transmission media, and much of the hardware and software. Code excited linear prediction (CELP) [1] is a speech coding method that has tremendous potential for providing the high quality that network voice applications demand for rates at and below 16 Kb/s. One difficulty with CELP is that it requires tremendous computational resources and memory for its codebook search. Just as there is a cost associated with the maximum bandwidth that a given network link can accommodate, there is a cost associated with the hardware necessary to support speech compression. With new telecommunications technologies promising to significantly reduce the cost of network bandwidth, the cost of the speech processing hardware may someday become the single most important consideration. Since digital signal processing chips (DSPs) and the fast memory chips supporting them consume a relatively major portion of a speech coding board’s real estate and power consumption, coding schemes that reduce the number of required DSPs and memory will significantly reduce the overall cost of a network.