Abstract
By means of the user-defined attribute, VHDL allows the user to annotate his or her description with information that can be extracted and processed by tools. In synthesis for example, user-defined attributes have been successfully used to convey timing and area constraints to tools. In VHDL’92, this capability is extended by allowing all statements to be labeled and thus annotated. Still, user-defined attributes apply only to single entities9 and not to groups of related items. So they fail to express in a clean way information such as pin-to-pin delay constraints.
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© 1993 Springer Science+Business Media New York
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Bergé, JM., Fonkoua, A., Maginot, S., Rouillard, J. (1993). Groups. In: VHDL’92. The Springer International Series in Engineering and Computer Science, vol 229. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3246-0_7
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DOI: https://doi.org/10.1007/978-1-4615-3246-0_7
Publisher Name: Springer, Boston, MA
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