Abstract
In VHDL, generic parameters, port declarations, and subprogram parameters are described by interface lists. It is not really clear in VHDL’87 whether or not a given formal can be referenced in the declaration of another formal when both appear in the same interface list. To illustrate this, consider the specification of an adder. It may be tempting to write it as
entity GENERAL_ADDER is port(A : BIT_VECTOR; B : BIT_VECTOR(A’RANGE);S : BIT_VECTOR(0 to A’LENGTH)); end GENERAL_ADDER; or, if a concurrent procedure call is preferred, as procedure GENERAL_ADDER( signal A : BIT_VECTOR; signal B : BIT_VECTOR(A’RANGE); signal S : out BIT_VECTOR(0 to A’LENGTH));
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© 1993 Springer Science+Business Media New York
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Bergé, JM., Fonkoua, A., Maginot, S., Rouillard, J. (1993). Interface List. In: VHDL’92. The Springer International Series in Engineering and Computer Science, vol 229. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3246-0_32
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DOI: https://doi.org/10.1007/978-1-4615-3246-0_32
Publisher Name: Springer, Boston, MA
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