Abstract
VHDL provides concurrent statements to document parallel operations or to abstractly model an ultimate circuit in a behavioral manner. These statements can be executed by a simulator at the same simulated time. The PROCESS statement is the primary concurrent statement in VHDL. Within a process, sequential statements specify the step-by-step behavior of the process. The dataflow style (shown in Chapter 6) is a shorthand form for the VHDL process.
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© 1993 Springer Science+Business Media New York
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Mazor, S., Langstraat, P. (1993). Sequential Statements. In: A Guide to VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3216-3_3
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DOI: https://doi.org/10.1007/978-1-4615-3216-3_3
Publisher Name: Springer, Boston, MA
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Online ISBN: 978-1-4615-3216-3
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