Abstract
The designers of the next generation of VLSI digital circuits are facing a range of problems such as clock skew, scalability, modularity, and power consumption, that seem to be intractable using the current synchronous design methodologies. One way to alleviate or possibly avoid these problems is to shift from the well-established clock-based synchronous design methodology to the relatively new self-timing-based asynchronous design methodology.
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© 1993 Springer Science+Business Media New York
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Lavagno, L., Sangiovanni-Vincentelli, A. (1993). Conclusions. In: Algorithms for Synthesis and Testing of Asynchronous Circuits. The Springer International Series in Engineering and Computer Science, vol 232. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3212-5_8
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DOI: https://doi.org/10.1007/978-1-4615-3212-5_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6410-8
Online ISBN: 978-1-4615-3212-5
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