Abstract
The synthesis algorithm described in Chapter 6 produces a circuit implementation that is guaranteed to be hazard-free if and only if a set of inequalities among path delays inside the circuit is satisfied. So using a suitable delay model during the synthesis process it is possible to guarantee hazard-freeness in the absence of delay faults. Now our goal is to test those path delays, and be sure that the above mentioned inequalities are satisfied in each manufactured circuit.
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© 1993 Springer Science+Business Media New York
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Lavagno, L., Sangiovanni-Vincentelli, A. (1993). The Design For Testability Methodology. In: Algorithms for Synthesis and Testing of Asynchronous Circuits. The Springer International Series in Engineering and Computer Science, vol 232. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3212-5_7
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DOI: https://doi.org/10.1007/978-1-4615-3212-5_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6410-8
Online ISBN: 978-1-4615-3212-5
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