Abstract
This chapter describes a synthesis procedure that transforms a correct Signal Transition Graph specification withComplete State Codinginto a logic circuit implementing it. The implementation can be shown to be hazard-free, using thebounded wiredelay model if:
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the circuit operates in an environment that obeys the STG specification, and
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the bounds on the delays are met by the circuit after manufacture.
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© 1993 Springer Science+Business Media New York
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Lavagno, L., Sangiovanni-Vincentelli, A. (1993). The Synthesis Methodology. In: Algorithms for Synthesis and Testing of Asynchronous Circuits. The Springer International Series in Engineering and Computer Science, vol 232. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3212-5_6
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DOI: https://doi.org/10.1007/978-1-4615-3212-5_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6410-8
Online ISBN: 978-1-4615-3212-5
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