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Introduction

Chapter

Abstract

Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. This book deals with methods of automatic verification as applied to computer hardware.

Keywords

Model Check Temporal Logic Finite State Machine Formal Verification Binary Decision Diagram 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  1. 1.Carnegie Mellon UniversityAustralia

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