Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. This book deals with methods of automatic verification as applied to computer hardware.
KeywordsModel Check Temporal Logic Finite State Machine Formal Verification Binary Decision Diagram
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