Skip to main content
SpringerLink
Log in
Book cover

Digital BiCMOS Integrated Circuit Design pp 329–393Cite as

BiCMOS Digital Circuit Applications

  • Chapter

  • 203 Accesses

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 193))

Abstract

In this chapter we study the application of BiCMOS digital circuits in the implementation of building blocks such as adders, ALU’s, memories, PLA’s and standard cells. The objective is to identify some of the applications where the BiCMOS can be useful. We will consider different design styles for BiCMOS circuits.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, Reading, MA (1985).

    Google Scholar 

  2. W. Heimsch, et al., “Merged CMOS/Bipolar Current Switch Logic (MCSL),” IEEE Journal of Solid-State Circuits, Vol. SC-24 pp. 1307–1311 (Oct. 1989).

    Article  Google Scholar 

  3. T. Hotta, et al., “A 70MHz-32b Microprocessor with 1.0um BiCMOS Macrocell Library,” International Solid-State Circuits Conference Tech. Dig. pp. 124–125 (Feb. 1989).

    Google Scholar 

  4. T. Hotta, et al., “1.3 pm CMOS/Bipolar Macrocell Library for VLSI Computers,” IEEE Journal of Solid-State Circuits, SC-23, No. 2 pp. 500–506 (Apr. 1988).

    Article  Google Scholar 

  5. G.P. Rosseel, et al., “A Single-Ended BiCMOS Sense-Circuit for Digital Circuits,” International Solid-State Circuits Conference Tech. Dig., pp. 114–115 (February 1989).

    Google Scholar 

  6. M. AnnaratoneDigital CMOS Design, Kluwer Academic Publishers (1986).

    Book  Google Scholar 

  7. K. HwangComputer Arithmetic: Principles, Architecture, and Design, John Wiley & Sons (1979).

    Google Scholar 

  8. K. Kurita, et al., “Very High-Speed ROM using Bipolar/CMOS Technology,” Electronics and Communications in Japan, Vol. 71 pp. 18–26 (1988).

    Google Scholar 

  9. T. Ikeda, A. Watanabe, Y. Nishio, I. Masuda, N. Tamba, M. Okada, and K. Ogiue, “High-Speed BiCMOS Technology with a Buried Twin Well Structure,” IEEE Trans. on Electron Devices, Vol. ED-34, No. 6 pp. 1304–1309 (June 1987).

    Article  Google Scholar 

  10. R.A. Kertis, et al., “A 12-ns ECL I/O 256Kx1-bit SRAM using a 1-pm BiCMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. SC-23 pp. 1048–1053 (Oct. 1988).

    Article  Google Scholar 

  11. H. Tran, et al., “An 8-ns 256K SRAM with CMOS Memory Array and Battery Backup Capability,” IEEE Journal of Solid-State Circuits, Vol. SC-23 pp. 1041–1047 (Oct. 1988).

    Article  Google Scholar 

  12. H. Tran, et al., “An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array size,” International Solid-State Circuits Conference Tech. Dig., pp. 36–37 (Feb. 1989).

    Google Scholar 

  13. M. Takada, et al., “A 5-ns 1-Mb ECL BiCMOS SRAM,” IEEE Journal of Solid-State Circuits, Vol. SC-25 pp. 1057–1062 (Oct. 1990).

    Article  Google Scholar 

  14. M. Suziki, et al., “A 3.5-ns, 500-mW 16-kbit BiCMOS ECL SRAM,” IEEE Journal of Solid-State Circuits, Vol. SC-24 pp. 1233–1237 (Oct. 1989).

    Article  Google Scholar 

  15. W. Heimsch, et al., “A 3.8-ns 16k BiCMOS SRAM,” IEEE Journal of Solid-State Circuits, Vol. SC-25 pp. 48–54 (Feb. 1990).

    Article  Google Scholar 

  16. S. Miyaoka, et al., “A 7-ns, 350-mW 64-kbit ECL-Compatible RAM,” IEEE Journal of Solid-State Circuits, Vol. SC-22 pp. 847–849 (Oct. 1987).

    Article  Google Scholar 

  17. M. Kubo et al., “Perspective on BiCMOS VLSI’s,” IEEE Journal of Solid-State Circuits, pp. 5–11 (Feb. 1988).

    Google Scholar 

  18. T. Douseki et. al., `BiCMOS Circuit Technology for a High-Speed SRAM,“ IEEE Journal of Solid-State Circuits, pp. 68–73 (Feb. 1988).

    Google Scholar 

  19. G. Kitsukawa, et al., “An Experimental 1-Mb BiCMOS DRAM,” IEEE Journal of Solid-State Circuits, Vol. SC-22 pp. 657–662 (Oct. 1987).

    Article  Google Scholar 

  20. S. Watanabe, et al., “BiCMOS Circuit Technology for High Speed DRAMs,” Symposium on VLSI Circuits Dig. Tech., pp. 79–80 (1987).

    Google Scholar 

  21. G. Kitsukawa, et al., “A 1-Mb BiCMOS DRAM using Temperature Compensation Circuit Techniques,” IEEE Journal of Solid-State Circuits, Vol. SC-24 pp. 597–602 (June 1989).

    Article  Google Scholar 

  22. T. Watanabe, et al, “Comparison of CMOS and BiCMOS 1-Mb DRAM Performance,” IEEE Journal of Solid-State Circuits, Vol. SC-24 pp. 771–778 (June 1989).

    Article  Google Scholar 

  23. G. Kitsukawa, et al., “A 23-ns 1-Mb BiCMOS DRAM,” IEEE Journal of Solid-State Circuits, Vol. SC-25 pp. 1102–1111 (Oct. 1990).

    Article  Google Scholar 

  24. K. Itoh, “Trends in Megabit DRAM Circuit Design,” IEEE Journal of Solid-State Circuits, Vol. SC-25 pp. 778–788 (June 1990).

    Article  Google Scholar 

  25. H. Kadota, et al., “A 32-bit Microprocessor with On-Chip Cache and TLB,” IEEE Journal of Solid-State Circuits, Vol. SC-22 pp. 800–807 (Oct. 1987).

    Article  Google Scholar 

  26. A.J. Smith, “Cache Memories,” Computing Surveys, Vol. 14 pp. 473–530 (Sept. 1982).

    Article  Google Scholar 

  27. L. Tamura, et al., “A 4-ns BiCMOS TLB,” IEEE Journal of Solid-State Circuits, Vol. SC-25 pp. 1093–1101 (Oct. 1990).

    Article  Google Scholar 

  28. C.A. Mead, and L.A. Conway, Introduction to VLSI Systems, Addison-Wesley (1980).

    Google Scholar 

  29. R.W. Sherbume, et al., “Datapath Design for RISC,” Proc. Conf. Advanced Research in VLSI, pp. 53–62 (1982).

    Google Scholar 

  30. R.W. Sherburne, et al., “A 32-bit NMOS Microprocessor with a Large Register File,” IEEE Journal of Solid-State Circuits, Vol. SC-19 pp. 682–689 (Oct. 1984).

    Article  Google Scholar 

  31. F. Murabayashi et al., “A 0.5 micron BiCMOS Channelless Gate Array,” IEEE Custom Integrated Circuits Conference Tech. Dig., pp. 8.7.1–8.7.4 (1989).

    Google Scholar 

  32. J. D. Gallia et al., “High-Performance BiCMOS 100K-Gate Array,” IEEE Journal of Solid-State Circuits, pp. 142–149 (FEb. 1990).

    Google Scholar 

  33. A. El Gamal et al., “B1NMOS: A Basic Cell for BiCMOS Sea-of-Gates,” IEEE Custom Integrated Circuits Conference Tech. Dig., pp. 8.3.1–8.3.4 (1989).

    Google Scholar 

  34. T. Hanibuchi et al., “A Bipolar-PMOS Merged Basic Cell for 0.8 micron BiCMOS Sea of Gates,” IEEE Journal of Solid-State Circuits, pp. 427–431 (March 1991).

    Google Scholar 

  35. H. Hara et al., “A 350 ps 50K 0.8 micron BiCMOS Gate Array with Shared Bipolar Cell Structure,” IEEE Custom Integrated Circuits Conference Tech. Dig., pp. 8.5.1–8.5.4 (1989).

    Google Scholar 

  36. P.P. Duchene and M.J. Declercq, “Strategies for CMOS/BiCMOS Gate Usage on Sea-of-Gates Arrays,” IEEE Custom Integrated Circuits Conference Tech. Dig., pp. 14.2.1–14.2.4 (1991).

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Texas A & M University, USA

    Sherif H. K. Embabi

  2. University of Waterloo, Canada

    Abdellatif Bellaouar & Mohamed I. Elmasry

Authors
  1. Sherif H. K. Embabi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Abdellatif Bellaouar
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mohamed I. Elmasry
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 1993 Springer Science+Business Media New York

About this chapter

Cite this chapter

Embabi, S.H.K., Bellaouar, A., Elmasry, M.I. (1993). BiCMOS Digital Circuit Applications. In: Digital BiCMOS Integrated Circuit Design. The Springer International Series in Engineering and Computer Science, vol 193. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3174-6_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-3174-6_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6391-0

  • Online ISBN: 978-1-4615-3174-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation