Abstract
In this paper, we review mathematical models that have been developed for improving the performance of a wafer fab that faces yield uncertainty and system uncertainty such as machine failures. Specifically, we focus on models that deal with the design and operational issues arising from a wafer fab. We classify these models into two main categories: yield models and wafer-design models. These models address different strategic and planning issues that related to yield uncertainty and system uncertainty in IC manufacturing, and can be used to predict system performance of a specific production plan or system design. Besides the predictive power, these models can be used for optimization.
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References
Albin, S.L. and D.J. Friedman, (1989), “The Impact of Clustered Defect Distributions in IC Fabrication,” Management Science, 35, 9, 1066–1078.
Ansley, W.G., (1968), “Computation of integrated-circuit yields from the distribution of slice yields for the individual devices,” IEEE Trans. Electron Devices, vol ED-15, pp 405–406, June.
Avram and Wein, (1990), “A Product Design Problem in Semiconductor Manufacturing,” Working Paper, Sloan School of Management, MIT.
Balcer, Y., and S. Lippman, (1984), “Technological Expectations and Adoption of Improved Technology,” Journal of Economic Theory, pp. 292–318.
Burman et al., (1986), “Performance Analysis Techniques for IC Manufacturing Lines,” AT&T Technical Journal, pp. 46–57.
Chen et al., (1988), “Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication,” Operations Research, pp. 202–215
Dennard, R.H., (1966), “Cost Study for Integrated Circuits with Many Logical Decisions per Chip,” Research Report RC-1552, IBM Thomas J. Watson Research Center, Yorktown Heights, NY.
Glaser and Dobberpuhl, (1985), Design and Analysis of VLSI Circuits, Addison-Wesley.
Graf, (1984), “Testing-A major concern for VLSI,” Solid State Technology, Jan, pp. 101–107.
Hamilton and Howard, (1975), Basic Integrated Circuit Engineering, McGraw-Hill Book Company.
Healy, (1981), Automated Testing and Evaluation of Digital Integrated Circuits, Reston Publishing.
Lawson, R.T., Jr., (1966), “A Prediction of th Photoresist Influence on Integrated Circuit Yield,” Semicond. Prod. Solid State Technol. 9, 22.
Marcus, (1981), “Diagnostic Techniques,” in VLSI Technology, edited by Sze, McGraw Hill.
Meyer, F., and Pradham D., (1989), “Modelling Defect Spatial Distribution,” IEEE Transactions on Computers, pp. 538–546.
Moore, G.E., (1970), Electronics, vol 43, p 126, Feb. 1970.
Murphy, B.T., (1964), “Cost Size Optima of Monolithic Integrated Circuits,” Proc. IEEE, 52, pp. 1537–1545.
Paz, O., and T.R. Lawson, Jr., (1977), “Modeling Defects Induced by Diffusion,” IEEE J. Solid-State Circuits, SC-12, 540–546.
Reinhard, (1987), Introduction to Integrated Circuit Engineering, Houghton Mifflin Company.
Seeds, R.B., (1967), “Yield, economic and logistic models for complex digital arrays,” in 1967 IEEE Int. Conv. Rec., part 6, Oct. 1967, p. 60.
Shimkunas, A., (1984), “Advances in X-Ray Mask Technology,” Solid State Technology, pp. 192–199.
Singh, M., C. Abraham, and R. Akella, (1990), “Planning for Production of a Set of Components when Yield is Random,” IEEE Transactions on CHMT, March issue.
Stapper, C.H., P. Castricci, R. Maeder, W. Rowe, and R. Verhelst, (1982), “Evolution and Accomplishments of VLSI Yield Management at IBM,” IBM J. Research & Development, Vol. 26, 5, pp. 532–545.
Stapper, (1985), “The Effects of Wafer to Wafer Defect Density Variations on Integrated Circuit Defect and Fault Distributions,” IBM Journal of Research and Development, pp. 87–97.
Stapper, C.H., (1986), “On yield, fault distributions, and clustering of particles” IBM J. Res. & Development, Vol. 30, 3, pp. 326–338.
Stapper, (1987), “Correlation Analysis of Particle Clusters on Integrated Circuit Wafers,” IBM Journal of Research and Development, pp. 641–650.
Tang, C., (1990), “Composing Batches with Yield Uncertainty,” Working Paper, UCLA, also to appear in European Journal of Operational Research.
Tang, C., (1991), “Designing an Optimal Production System with Inspection,” European Journal of Operational Research, pp. 45–54.
Warner, R.M., (1974), “Applying a Composite Model to the IC yield problem,” IEEE J. Solid-State Circuits, SC-9, 86–95 (June).
Wilson, A., (1986), “X-Ray Lithography: can it be justified?” Solid State Technology, pp. 249–255.
Yanagawa, T., (1972) “Yield degradation of integrated circuits due to spot defects,” IEEE Trans. Electron Devices, vol ED-19, pp 190–197, Feb.
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Tang, C.S., Demeester, L. (1993). Mathematical Models in Integrated-Circuit Manufacturing: A Review. In: Sarin, R.K. (eds) Perspectives in Operations Management. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3166-1_20
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DOI: https://doi.org/10.1007/978-1-4615-3166-1_20
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