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An Analytical Model for ATM Based Networks Which Utilize Look-Ahead Contention Resolution Switching

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Local Area Network Interconnection

Abstract

Interconnection of multiple media sources will be handled by ATM based networks in B-ISDN systems. These ATM networks act as a backbone for subnetworks (such as LANs, MANs, etc). These subnetworks hold individual media or wholly integrated subsets of the necessary data. This paper will present a new analytical model describing the behavior of ATM based interconnection networks which utilize a scheme called Look-Ahead Contention Resolution (LCR). to reduce packet collision and thereby increase throughput. To the knowledge of the authors, this is the only analytical model in the current literature that addresses the LCR. problem. The switches modeled in this work are output queued and are non-lossy. The analytical model gives a set of closed-form equations which lead to an iterative solution for normalized bandwidth and normalized delay for networks in which the queues are searched to a depth of k. (DOS = k.) where 1 ≤ k ≤ sizeof(queue). in order to find a successful candidate for packet transmission during a network cycle. The model provides results which are very accurate compared to simulation results even under very high loads.

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References

  1. Jianxun Ding and Laxmi N. Bhuyan, “Performance Evaluation of Multistage Interconnection Networks with Finite Buffers”, In Proceedings of the 1991 International Conference on Parallel Processing., pages I-592 - I-599, St. Charles, IL, August 1991, CRC Press, Inc.

    Google Scholar 

  2. Daniel M. Dias and J. Robert Jump, “Analysis and Simulation of Buffered Delta Networks”, IEEE Transactions on Computers.,C-30(4):273–282, April 1981.

    Article  Google Scholar 

  3. Michael G. Hluchyj and Mark J. Karol, “Queueing in High-Performance Packet Switching”, IEEE Journal on Selected Areas in Communications.,6(9):1587–1597, DEcember 1988.

    Article  Google Scholar 

  4. Hong Jiang, Laxmi N. Bhuyan, and Jogesh K. Muppala, “MVAMIN: Mean Value Analysis Algorithms for Multistage Interconnection Networks”, Journal of Parallel and Distributed Computing.,(12):189–201, December 1991.

    Article  MATH  Google Scholar 

  5. Yih-Chyun Jenq, “Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network”, IEEE Journal on Selected Areas in Communications., SAC-1(6):1014–1021, December 1983.

    Article  Google Scholar 

  6. Mark J. Karol, Michael G. Hluchyj, and Samuel P. Morgan, “Input Versus Output Queueing on a Space-Division Packet Switch”, IEEE Transactions on Communications., COM-35(12):1347–1356, December 1987.

    Article  Google Scholar 

  7. Clyde P. Kruskal and Marc Snir, “The Performance of Multistage Interconnection Networks for Multiprocessors”, IEEE Transactions on Computers., C-32(12):1091–1098, December 1983.

    Article  Google Scholar 

  8. Clyde P. Kruskal, Marc Snir, and Alan Weiss, “On the Distribution of Delays in Buffered Multistage Interconnection Networks for Uniform and Nonuniform Traffic”, In Proceedings of the 198.E International Conference on Parallel Processing., pages 215–219, Bellaire, MI, August 1984.

    Google Scholar 

  9. Clyde P. Kruskal, Marc Snir, and Alan Weiss, “The Distribution of Waiting Times in Clocked Multistage Interconnection Networks”, In Proceedings of the 1986 International Conference on Parallel Processing.,pages 12–19, University Park, PA, August 1986, IEEE Computer Society Press.

    Google Scholar 

  10. Clyde P. Kruskal, Marc Snir, and Alan Weiss, “The Distribution of Waiting Times in Clocked Multistage Interconnection Networks”, IEEE Transactions on Computers., C-37(11):1337–1352, November 1988.

    Article  MathSciNet  MATH  Google Scholar 

  11. Janak H. Patel, “Performance of Processor-Memory Interconnections for Multiprocessors”, IEEE Transactions on Computers., C-30(10):771–780, October 1981.

    Article  Google Scholar 

  12. Ken W. Sarkies, “The Bypass Queue in Fast Packet Switching”, IEEE Transactions on Communications.,39(5):766–774, May 1991.

    Article  Google Scholar 

  13. Yoshito Sakurai, Nobuhiko Ido, Shinobu Gohara, and Noboru Endo, “Large-Scale ATM Multistage Switching Network with Shared Buffer Memory Switches”, IEEE Communications Magazine., (1):90–96, January 1991.

    Google Scholar 

  14. Hyunsoo Yoon, Kyungsook Y. Lee, and Ming T. Liu, “Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems”, IEEE Transactions on Computers., 39(3):319–327, March 1990.

    Article  Google Scholar 

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© 1993 Springer Science+Business Media New York

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Luciani, J.V., Chen, C.Y.R. (1993). An Analytical Model for ATM Based Networks Which Utilize Look-Ahead Contention Resolution Switching. In: Onvural, R.O., Nilsson, A. (eds) Local Area Network Interconnection. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2950-7_7

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  • DOI: https://doi.org/10.1007/978-1-4615-2950-7_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6282-1

  • Online ISBN: 978-1-4615-2950-7

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