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Architecture and Performance Evaluation for High Speed LAN Internetworking Processors

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Local Area Network Interconnection

Abstract

High-performance internetworking processors are inevitable in realizing multimedia communications on gigabit internets. This paper compares various alternative architecture in term of performance and functionality, and proposes an optimal architecture of high-performance internetworking processors, referred to as INP (Internetwork Nodal Processors), which can forward packets at the network layer protocol. INPs are basically composed of two main components: 1) several network I/F modules which perform network layer functions, and 2) a data forwarding module which interconnects the network I/F modules and provides message paths between any pair of them. First, three types of INP architecture are compared in considering allocation methods for various tables used for route decision. Next, showing performance bottleneck caused by a bus based INP architecture, INPs using a switch for data forwarding modules are analyzed. For the switch architecture, three alternative packet buffering schemes are compared. Through these comparisons, this paper proposes that a combination of the table allocation fully distributed on network I/F modules and an input-output buffer switch for a data forwarding module is best-suited for high-performance INPs.

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© 1993 Springer Science+Business Media New York

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Taniguchi, K., Suzuki, H., Nishida, T. (1993). Architecture and Performance Evaluation for High Speed LAN Internetworking Processors. In: Onvural, R.O., Nilsson, A. (eds) Local Area Network Interconnection. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2950-7_13

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  • DOI: https://doi.org/10.1007/978-1-4615-2950-7_13

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6282-1

  • Online ISBN: 978-1-4615-2950-7

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