Conclusions

Abstract

The role of packaging has grown dramatically in importance in the past few years, and high-performance packages such as multichip modules have become increasingly popular. Careful design of these packages can significantly increase the benefits they provide.

A considerable body of literature on physical design problems in VLSI exists. The first objective of this book was to provide the reader with a clear understanding of what an MCM is, and how it differs physically from a VLSI chip. Chapter 1 gave an overview of the various technologies, features and design problems associated with MCMs, and provided the background for the material discussed in the following chapters.

The physical design of a VLSI chip involves a large number of active and passive devices and interconnections, often with variable sizes, shapes and locations which can be adjusted for optimum performance. In contrast, MCM physical design is focussed primarily on interconnections. Thus, interconnections form a natural starting point for the study of MCM physical design, and are discussed at length in Chapter 2. Unlike on-chip wires, which can be modeled fairly well as lumped capacitors, interchip wires have to be modeled as lossy transmission lines, which are notoriously difficult to analyze. The computational cost of accurate timing analysis of all the nets in an MCM can easily dominate the cost of the entire physical design process. New approaches to interconnect analysis are presented in Chapter 2, which can compute approximate time-domain responses of MCM interconnects. The rapid estimation approaches can provide excellent approximations of the time-domain response, while running as much as several hundred times faster than a conventional simulation program.

Chapter 2 also describes delay models for MCM interconnects. A new second-order delay model is developed for multiterminal interconnects, which is able to capture the effect of line inductance on net delays. Existing delay models are limited to RC models, which can be very optimistic when transmission line effects come into play.

The problems of system partitioning and chip placement are considered in Chapter 3. The partitioning and placement problems for VLSI have been studied intensively for several years, and several effective algorithms have been developed. However, none of these algorithms can be applied directly to MCMs, since they usually ignore timing constraints, or use delay models which are not appropriate for MCM interconnects. On-chip wires are short, and their resistance is usually negligible compared to the output impedance of the driver. However, MCM wires are much longer, and the output impedances of off-chip drivers are smaller than those of on-chip drivers. Thus, wire resistance cannot be ignored in performance-driven design of MCMs. This makes the MCM partitioning and placement problems much more complicated, since net delays depend on the actual net topology, in addition to the wire length. Chapter 3 describes timing-driven partitioning algorithms which are able to handle arbitrary delay models, and a resistance-driven placement algorithm, which takes wire resistance into account to find a placement minimizing interchip net delays. This algorithm is demonstrated to be capable of generating placements with significantly smaller net delays than conventional approaches, which ignore wire resistance.

The physical design step which follows placement is routing. MCM routing may involve many layers of wiring, unlike VLSI, where two or three layers usually suffice. In addition, MCM routing has unique features, such as segmented vias, and complex constraints such as transmission line effects, which make it necessary to use new routing algorithms developed specifically for MCMs. Chapter 4 describes some recent algorithms capable of handling the complexity of multilayer MCM routing.

Chapter 5 describes another popular approach to MCM routing, in which the multilayer problem is decomposed into two stages: two-dimensional routing and layer assignment. For the two-dimensional tree-generation problem, the conventional minimum Steiner tree heuristics used in VLSI are not adequate, since they ignore both wire resistance and inductance. Recent work on performance-oriented tree construction algorithms is presented, in which trees are constructed for minimizing first-or second-order delays.

Chapter 6 deals with the second stage of multilayer routing, layer assignment. Two approaches to the problem are considered. The first approach is based on a new model for the MCM-C multilayer routing environment, which allows such features as segmented vias and terminals on the top as well as the bottom layers. The second approach does not require a routing grid, and is hence more suitable for high-density MCMs, such as MCM-Ds. It is based on a graph partitioning problem on an “interference graph” generated from a netlist or a two-dimensional global routing. Techniques for constructing the interference graph and for minimizing crosstalk between nets are described.