Abstract
Macro Test relies on the availability of an access protocol for every leaf-macro from the device pinning such that the corresponding leaf-macro test can be executed from the pins of the device. Initially, information is required on how to test the leaf-macro as a stand-alone entity. This information is described in the leaf-macro initial test plans. As explained in Chapter 3, an initial test plan is independent of the actual leaf macro test pattern set and is needed for the testability synthesis of the design. Hence, before starting the testability synthesis phase a study is needed on how to test every leaf-macro as a stand-alone unit. This study is guided by the capabilities of the module compilers and libraries as residing in a design system or by the capabilities of a logic synthesis tool used. For example, the design system may have RAM, ROM, and PLA module compilers, or may have a logic synthesis tool which is capable of generating a fully scannable leaf-macro or a self-testable leaf-macro.
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© 1995 Springer Science+Business Media Dordrecht
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Beenker, F.P.M., Bennetts, R.G., Thijssen, A.P. (1995). Examples of Leaf-Macro Test Techniques. In: Testability Concepts for Digital ICs. Frontiers in Electronic Testing, vol 3. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2365-9_4
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DOI: https://doi.org/10.1007/978-1-4615-2365-9_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6004-9
Online ISBN: 978-1-4615-2365-9
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