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VLSI CMOS Subsystem Design

  • Abdellatif Bellaouar
  • Mohamed I. Elmasry

Abstract

In this chapter, we study the application of the circuit techniques developed through Chapter 4 in the implementation of CMOS building blocks such as adders, multipliers, ALUs, data-path, and regular structures, etc. The power dissipation constraint is also included through the several options presented for each circuit. The use of Phase locked Loop (PLL) in high-speed CMOS systems for deskewing the internal clock is also examined. Low-power issues of the circuits presented are also discussed.

Keywords

Power Dissipation Partial Product Phase Lock Loop Charge Pump Register File 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Abdellatif Bellaouar
    • 1
  • Mohamed I. Elmasry
    • 1
  1. 1.University of WaterlooCanada

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