Abstract
In this chapter, we study the application of the circuit techniques developed through Chapter 4 in the implementation of CMOS building blocks such as adders, multipliers, ALUs, data-path, and regular structures, etc. The power dissipation constraint is also included through the several options presented for each circuit. The use of Phase locked Loop (PLL) in high-speed CMOS systems for deskewing the internal clock is also examined. Low-power issues of the circuits presented are also discussed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Mori, et al., “A 10-ns 54 x 54-b Parallel Structured Full Array Multiplier with 0.5-µm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 600-606, April 1991.
J. Sklansky, “An Evaluation of Several Two-Summand Binary Adders,” IRE Transactions on Electronic Computers, vol. EC-9, pp. 213–226, June 1960.
J. Sklansky, “Conditional-Sum Addition Logic,” IRE Transactions on Electronic Computers, vol. EC-9, pp. 226–231, June 1960.
I. S. Abu-Khater, R. H. Yan, A. Bellaouar, and M. I. Elmasry, “A 1-V Low-Power High-Performance 32-b Conditional Sum Adder,” IEEE Symposium on Low-Power Electronics, Tech. Dig., San Diego, pp. 66–67, October 1994.
T. Sato, et al., “An 8.5ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 657–659, April 1992.
K. Ueda, H. Suziki, K. Suda, Y. Tasujihashi, H. Shinohara, “A 64-bit Adder By Pass Transistor BiCMOS Circuit,” IEEE Custom Integrated Circuit Conference, Tech. Dig., pp. 12.2.1–12.2.4, May 1993.
K. Hwang, “Computer Arithmetic: Principles, Architecture, and Design,” John Wiley and Sons, 1979.
J. J. F. Cavanagh, “Computer Science Series: Digital Computer Arithmetic,” McGraw-Hill Book Co., 1984.
M. Nagamatsu, S. Tanaka, J. Mori, T. Noguchi, and K. Hatanaka, “A 15-ns 32x32-bit CMOS Multiplier with an improved Parallel Structure,” IEEE Custom Integrated Circuits Conference, Tech. Dig., pp. 10.3.1–10.3.4, May 1989.
N. Ohkubo, M. Suziki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4-ns CMOS 54x54-b Multiplier using Pass-Transistor Multiplexer,” IEEE Custom Integrated Circuits Conference, Tech. Dig., pp. 599–602, May 1994.
R. Bechade, et al., “A 32b 66MHz Microprocessor,” IEEE International Solid-State Circuits Conference, Tech. Dig., pp. 208–209, February 1994.
C. A. Mead, and L. A. Conway, “Introduction to VLSI Systems,” Addison-Wesley, 1980.
R. W. Sherburne, et al., “Data path Design for RISC,” Proc. Conf. Advanced Research in VLSI, pp. 53–62, 1982.
R. W. Sherburne, et al., “A 32-bit NMOS Microprocessor with a Large Register File,” IEEE Journal of Solid-State Circuits, vol. SC-19, no. 5, pp. 682–689, October 1984.
K. J. O’Connor, “The Twin-Port Memory Cell,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 712–720, October 1987.
R. D. Jolly, “A 9-ns, 1.4-Gigabyte/s 17-Ported CMOS Register File,” IEEE Journal of Solid-State Circuits, vol. 26, no. 10, pp. 1407–1412, October 1991.
H. Shinohara, et al., “A Flexible Multiport RAM Compiler for Data Path,” IEEE Journal of Solid-State Circuits, vol. 26, no. 3, pp. 343–349, March 1991.
A. R. Linz, “A Low-Power PLA for a Signal Processor,” IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 107–115, February 1991.
G. M. Blair, “PLA Design for Single-Clock CMOS,” IEEE Journal of Solid-State Circuits, vol. 27, no. 8, pp. 1211–12113, August 1992.
H. Kadota, et al., “A 32-bit Microprocessor with On-Chip Cache and TLB,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 800–807, October 1987.
A. J. Smith, “Cache Memories,” Computing Surveys, Vol. 14, pp. 473–530, September 1982.
L. Ashby, “ASIC Clock Distribution using a Phase Locked Loop (PLL),” in IEEE International ASIC Conference and Exhibit, Tech. Dig., pp. P1.6.1–P1.6.3, September 1991.
F. M. Gardner, “Phase Lock Techniques,” John Wiley and Sons, 1979.
F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Transactions on Communications, COM-28(ll), pp. 1849–1858, November 1980.
R. E. Best, “Phase-Locked Loops,” McGraw Hill, 1984.
J. Goto, et al., “A Programmable Clock Generation with 50 to 350 MHz Lock Range for Video Signal Processors,” IEEE Custom Integrated Circuits Conference, Tech. Dig., pp. 4.4.1–4.4.4, May 1993.
I. A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599–1607, November 1992.
M. G. Johnson, and E. L. Hudson, “A Variable Delay Line PLL for CPU-Coprocessor Synchronization,” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, pp. 1218–1223, October 1988.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1995 Springer Science+Business Media New York
About this chapter
Cite this chapter
Bellaouar, A., Elmasry, M.I. (1995). VLSI CMOS Subsystem Design. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_7
Download citation
DOI: https://doi.org/10.1007/978-1-4615-2355-0_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5999-9
Online ISBN: 978-1-4615-2355-0
eBook Packages: Springer Book Archive